| PART |
Description |
Maker |
| BA7078AF1 BA7078AS BA7078AF BA7078AF-E2 |
Silicon Monolithic Integrated Circuit
Sync.Seperator/Sync. Detector IC for Multi-Sync. Monitor
|
ROHM[Rohm]
|
| MC100EL07DTR2 MC100EP33DR2 MC100EL38 |
5V ECL 2-Input XOR/XNOR
3.3V / 5V ECL ÷4 Divider
5V ECL Divide by 2, Divide by 4/6 Clock Generation Chip
|
ON Semiconductor
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| MC10H109FNR2 MC10H131 MC100EP140 MC100E155FN MC100 |
Dual 4-5-Input OR/NOR Gate
Dual Type D Master-Slave Flip-Flop
3.3V ECL Phase-Frequency Detector
5V ECL 6-Bit 2:1 Mux Latch
5V ECL Differential Data and Clock D Flip-Flop
3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3V ECL 1:15 Differential ÷1/÷2 Clock Driver
ECL/TTL Clock Driver
3.3V / 5V 2-Input Differential AND/NAND
5V ECL 2:1 Multiplexer
3.3V / 5V ECL JK Flip Flop
3.3V ECL 1:4 ÷ 1/÷ 2 Clock Fanout Buffer
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V 10-bit LVTTL/LVCMOS to LVPECL Translator
Dual 2-Bit Adder/Subtractor
|
ON Semiconductor
|
| EDI2AG272129V9D1 EDI2AG272129V10D1 EDI2AG272129V12 |
2x128Kx72, 3.3V,9ns, Sync/Sync Burst SRAM Module(2x128Kx72, 3.3Vns,同步/同步脉冲静态RAM模块)
2x128Kx72, 3.3V,10ns, Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V0ns,同步/同步脉冲静态RAM模块)
2x128Kx72, 3.3V,12ns, Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V2ns,同步/同步脉冲静态RAM模块)
2x128Kx72,, 3.3V,8.5ns, Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V.5ns,同步/同步脉冲静态RAM模块)
|
White Electronic Designs Corporation
|
| MC100EP01 MC10EP445 MC10H172FNR2 MC100EL29 MC100H6 |
3.3V / 5V ECL 4-Input OR/NOR
3.3V / 5VECL 8-Bit Serial/Parallel Converter
Dual Binary 1-4-Decoder (High)
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
9-Bit TTL-ECL Translator
Quad TTL-ECL Translator
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3V 10-bit LVTTL/LVCMOS to LVPECL Translator
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
5V ECL Voltage Controlled Oscillator
3.3V ECL D-Type Flip-Flop with Set and Reset
Binary to 1-8 Decoder (Low)
Differential -5V ECL To TTL Translator
-3.3V / -5V Triple ECL Input to PECL Output Translator
5V ECL Dual Differential 2:1 Multiplexer
Quad MSTR
5V ECL Quad 4-Input OR/NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
Dual 4-5-Input OR/NOR
|
ON Semiconductor
|
| EDI2CG472256V EDI2CG472256V10D2 EDI2CG472256V12D2 |
8 Megabyte Sync/Sync Burst, Dual Key DIMM
|
White Electronic Designs Corporation
|
| BUS-61570-830K BUS-61571-830K BUS-61571-XXXX BUS-6 |
MIL-STD-1553 Bc-rt-mt Integrated Terminal
Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
Small Signal Bias Resistor Transistor, PNP, 50 V
5 V ECL 2 Divider
9-Bit ECL to TTL Translator
2.5 V / 3.3 V ECL 2-Input Differential AND/NAND
MIL-STD-1553B NOTICE 2 ADVANCED INTEGRATED MUX HYBRIDS WITH ENHANCED RT FEATURES (AIM-HYer) 符合MIL - STD - 1553B总线公告2先进综合复用的杂交强化逆转录特征（枚AIM - HYer
5V ECL JK Flip-Flop 符合MIL - STD - 1553B总线公告2先进综合复用的杂交强化逆转录特征（枚AIM - HYer
5V ECL 2:1 Multiplexer 符合MIL - STD - 1553B总线公告2先进综合复用的杂交强化逆转录特征（枚AIM - HYer
|
List of Unclassifed Man...
Data Device
ETC[ETC]
List of Unclassifed Manufacturers
Electronic Theatre Controls, Inc.
http://
|
| WT9051 |
Sync Singal Processor for Multi-Sync Display
|
Weltrend Semiconductor
|
| UPC1884 UPC1884CT |
SYNC SIGNAL PROCESSOR FOR MULTI-SYNC DISPLAY
|
NEC
|
| MAX7461EUK |
The MAX7461 single-channel loss-of-sync alarm (LOS-bar) provides composite video sync detection in NTSC, PAL,
|
MAXIM
|
| GS88018BT-133 GS88018BT-133I GS88018BT-150 GS88018 |
133MHz 8.5ns 512K x 18 9Mb sync burst SRAM
150MHz 7.5ns 512K x 18 9Mb sync burst SRAM
166MHz 7ns 512K x 18 9Mb sync burst SRAM
200MHz 6.5ns 512K x 18 9Mb sync burst SRAM
225MHz 6ns 512K x 18 9Mb sync burst SRAM
250MHz 5.5ns 512K x 18 9Mb sync burst SRAM
|
GSI Technology
|
